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T CT DUC PRO PRODU TE OLE UTE OBS UBSTIT G4030J D S DataoSheet -2 r IBLE OSS HI1-5051 P
TM
IH5151
March 2000 File Number 3133.3
Dual SPDT, CMOS Analog Switch [ /Title (IH515 1) /Subject (Dual SPDT, CMOS Analog Switch ) /Autho r () /Keywords (Intersil Corporation, semiconductor, Dual SPDT, CMOS Analog Switch ) /Creator () /DOCI NFO pdfmark [
The IH5151 solid state analog switch is designed using an improved, high voltage CMOS technology. Key performance advantages in the IH5151 are TTL compatibility and ultra low power operation. rDS(ON) switch resistance is typically in the 14 to 18 area, for signals in the -10V to +10V range. Quiescent current is less than 10A. The IH5151 also guarantees Break-Before-Make switching which is logically accomplished by extending the tON time (200ns typical) such that it exceeds tOFF time (120ns typical). This insures that an ON channel will be turned OFF before an OFF channel can turn ON. The need for external logic required to avoid channel to channel shorting during switching is thus eliminated.
Features
* Low rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 * Switches Greater than 20VP-P Signals with 15V Supplies * Quiescent Current (Max) . . . . . . . . . . . . . . . . . . . . 100A * Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200ns * TTL, CMOS Compatible * Complete Monolithic Construction * Supply Range. . . . . . . . . . . . . . . . . . . . . . . . . 5V to 15V
Functional Diagram
SWITCH STATE SHOWN FOR LOGIC "1" INPUT
Part Number Information
PART NUMBER IH5151MJE TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld CERDIP PKG. NO. F16.3
VL 12 S1 16
V+ 11 1 D1 D3
Pinout
IH5151 (CERDIP) TOP VIEW
S3
4
3
IN1 15 IN2 10
D1 NC D3 S3 S4 D4 NC D2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
S1 IN1 VGND VL V+ IN2 S2 S2 S4 9 8 D2 D4
5 13 GND V14
6
TRUTH TABLE LOGIC 0 1 SWITCH 1, 2 Off On SWITCH 3, 4 On Off
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
IH5151 Schematic Diagram
ONE SET OF SWITCHES SHOWN
+15V (V+)
Q3
Q7
Q5
Q20 D +15V
Q18
4k 5k Q2 100 TTL IN Q1 Q8 3k Q9 GND Q10 +15V 5k Q4 Q6
Q19
S
VQ16 Q17
V+ Q12 +15V S Q11 Q15
VL = +5V
D
Q13
-15V (V-)
Q14
2
IH5151
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <22V VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 18 Maximum Junction Temperature CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, V- = -15V, VL = +5V (NOTES 3, 5)
PER CHANNEL PARAMETER DYNAMIC CHARACTERISTICS Turn ON Time, tON Turn OFF Time, tOFF Charge Injection, Q OFF Isolation, OIRR Crosstalk, CCRR DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) Input Logic Current, IIN(OFF) ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) Channel-to-Channel rDS(ON) Match, rDS(ON) Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, ID(OFF), IS(OFF) Switch ON Leakage Current, ID(ON)+IS(ON) POWER SUPPLY CHARACTERISTICS + Power Supply Quiescent Current, I+ - Power Supply Quiescent Current, I+5V Supply Quiescent Current, IL Ground Quiescent Current, IGND NOTES:
TEST CONDITIONS
-55oC
25oC
125oC
UNITS
RL = 1k, VANALOG = -10V to +10V; (Figure 6, Note 4) Figure 5 f = 1MHz, RL = 100, CL 5pF (Figure 3) Figure 2
-
10 (Typ) 54 (Typ) -54 (Typ)
500 250 -
ns ns mV dB dB
VIN = 2.4V (Note 2) VIN = 0.8V (Note 2) VD = 10V, IS = -10mA
1 1
1 1
10 10
A A
25 -
25 10 (Typ) 14 (Typ) 1.0 1.0
50 100 100
V nA nA
VANALOG = -10V to +10V VD = VS = -10V to +10V
-
10 10 10 10
10 10 10 10
100 100 100 100
A A A A
2. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Refer to logic diagrams to find logical value of logic input required to produce ON or OFF state. 3. Typical values are for design aid only, not guaranteed or production tested. 4. For IH5151 devices, channels which are off for logic input 2.4V (Pins 3 and 4, 5 and 6) have slower tON time, than channels on Pins 1, 16 and 8, 9. This is done so switch will maintain break-before-make action when connected in DT configuration, i.e., Pin 1 connected in Pin 3. 5. Min or Max value, unless otherwise specified.
3
IH5151 Test Circuits and Waveforms
100 90 80 70 rDS(ON) () 60 50 40 30 20 10 0 -12 -10 -8 -6 -4 -2 0 2 VANALOG (V) 4 6 8 10 12 5V SUPPLIES 15V SUPPLIES
FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE
-120 CCRR = 20LOG -100 CROSSTALK (dB) VOUT (mVP-P) 2000mVP-P OFF STATE -80 100 VOUT
-60
-40 ON STATE 2VP-P AT 1MHz 51 0 1 10 100 1K 10K FREQUENCY (Hz) 100K 1M 100
-20
FIGURE 2A. CROSSTALK vs FREQUENCY FIGURE 2. CROSSTALK
FIGURE 2B. TEST CIRCUIT
120 OIRR = 20LOG 100 OFF ISOLATION (dB)
2000mVP-P VOUT (mVP-P)
80 2VP-P AT 1MHz
60
51
40 OFF STATE 20 100 1 10 100 1K 10K FREQUENCY (Hz) 100K 1M VOUT
0
FIGURE 3A. OFF ISOLATION vs FREQUENCY FIGURE 3. OFF ISOLATION
FIGURE 3B. TEST CIRCUIT
4
IH5151 Test Circuits and Waveforms (Continued)
2000 IQUIESCENT (EITHER + OR - SUPPLY) (A)
200 3V LOGIC INPUT 0V 0.1T 20 T I T
=
2 1 10 100 1K 10K 100K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz)
FIGURE 4A. SUPPLY CURRENT vs FREQUENCY
FIGURE 4B. LOGIC INPUT WAVEFORM
FIGURE 4. SUPPLY CURRENT vs LOGIC FREQUENCY
VOUT A 1 10pF 1k 2 ANALOG INPUT 3V 0V LOGIC INPUT 10nF VOUT VOUT B 3 4 5 6 7 8 10pF 1k 15 14 -15V 13 0V 12 +5V 11 +15V 10 9 10V tON tOFF 0V -10V VOUT +3V LOGIC INPUT 16 tON tOFF VOUT
10V 0V
+10V
FIGURE 5. CHARGE INJECTION TEST CIRCUIT
FIGURE 6. tON AND tOFF TEST CIRCUIT AND MEASUREMENT POINTS
Typical Applications
Nulling Out Charge Injection
Charge injection (QINJ on spec. sheet) is caused by gate to drain, or gate to source capacitance of the output switch MOSFETs. The gates of these MOSFETs typically swing from -15V to +15V as a rapidly changing pulse; thus this 30VP-P pulse is coupled through gate capacitance to output load capacitance, and the output "step" is a voltage divider from this combination. For example:
C GATE Qinject (V P-P ) ------------------- x 30V step. C LOAD
To null this error step out to zero the circuit in Figure 7 can be used.
27pF
1000pF S&H CAPACITOR
1 2 3 4 5 6 7 8
16 0V 15 14 13 12 +5V 11 +15V 10 9 -15V
3V TTL STROBE 50K POT
i.e.,
C GATE = 1.5pF, C LOAD = 1000pF, then 1.5pF Qinject (V P-P ) = -------------------- x 30V step = 45mV P-P 1000pF
Thus if you are using a switch in a Sample and Hold application with CSAMPLE = 1000pF, a 45mVP-P "Sampleto-Hold Error Step" will occur. 5
FIGURE 7. ADJUSTABLE CHARGE INJECTION COMPENSATION CIRCUIT
IH5151
The circuit in Figure 7 nulls out charge injection effects on switch pins 1 and 16; a similar circuit would be required on switch pins 8 and 9. Simply adjust the pot until VOUT = 0mVP-P pulse, with VANALOG = 0V. If you do not desire to do any adjusting, but wish the least amount of charge injection possible, then the circuit in Figure 8 should be used.
27pF
Fault Condition Protection
If your system has analog voltage levels which are independent of the 15V (Power Supplies), and these analog levels can be present when supplies are shut off, you should add fault protection diodes as shown in Figure 9. If the analog input levels are below 15V, the PN junctions of Q13 and Q15 are reversed biased. However if the 15V supplies are shut off and analog levels are still present, the configuration becomes as shown in Figure 10. The need for the diodes in this circumstance is shown in Figure 11. If ANALOG INPUT is greater than 1V, then the PN junction of Q15 is forward biased and excessive current will be drawn. The addition of 1N914 diodes prevents the fault currents from destroying the switch. A similar event would occur if ANALOG INPUT was less than or equal to -1V, wherein Q13 would become forward biased. The 1N914 diodes form a "back to back" diode arrangement with Q13 and Q15 bodies. This structure provides a degree of overvoltage protection when supplies are on normally, and analog input level exceeds supplies. This circuit will switch up to about 8V ANALOG overvoltages. Beyond this drain (N) to body (P) breakdown VOLTAGE of Q13 limits overvoltage protection.
FROM DRIVER
1000pF S&H CAPACITOR
1 2 3 4 5 6 7 8
16 15 14 13 12 +5V 11 +15V 10 9
3V 0V TTL 10 STROBE k
39k -15V
FIGURE 8. NO-ADJUST CHARGE INJECTION COMPENSATION CIRCUIT
This configuration will produce a typical charge injection of VOUT 10mVP-P into the 1000pF S & H capacitor shown.
1 2 3 4 5 6 7 8
16 P 15 14 13 12 +5V 1N914 11 5 10 9 FROM DRIVER +15V 1N914 -15V 1 Q15 N +15 P
ANALOG INPUT 16
OUTPUT SWITCH PAIR -15V Q13 N P N
FIGURE 9. ADDING DIODES PROTECTS SWITCH
FIGURE 10. SWITCH WITHOUT PROTECTION DIODES
Q15 P N 0V WHEN +15V SUPPLY SHUT OFF 1 0V WHEN -15V IS SHUT OFF P N N Q 13 N ANALOG INPUT 16 SAY -10V TO +10V 16 P P
Q15 P N 1N914 +15V -15V 1N914 P N Q13 OVERVOLTAGE ANALOG INPUT 1
FIGURE 11. FAULT CONDITION WITHOUT PROTECTION DIODES
FIGURE 12. FAULT CONDITION WITH PROTECTION DIODES
6
IH5151 Die Characteristics
DIE DIMENSIONS: 2515m x 3074m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
IH5151
PIN 5 S4 PIN 6 D4 PIN 4 S3 PIN 3 D3
PIN 8 D2
PIN 1 D1
PIN 9 S2
PIN 6 S1
PIN 10 IN2 PIN 11 PIN 12 V+ VL SUBSTRATE PIN 13 GND PIN 14 V-
PIN 5 IN1
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 7

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